View TS3000GB0A0_8353932.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 of 25 november 4, 2014 ? 2014 integrated device technology, inc. dsc 7332/8 ? idt and the idt logo are regi stered trademarks of integrated device technology, inc. description the TS3000GB0A0 digital temperature sensor with accuracy up to 0.5c was designed to target applications demanding highest level of temperature readout. the sensor is fully compliant with jedec jc42.4 component specification. the digital temperature sensor come s with several user-programmable registers to provide maximum flex ibility for temperature-sensing applications. the registers allow sp ecifying critical, upper, and lower temperature limits as well as hyst eresis settings. both the limits and hysteresis values are used for comm unicating temperature events from the chip to the system. this communication is done using the event pin, which has an open-drain configuration. the user has the option of setting the event pin polarity as either an active -low or active-high comparator output for thermostat operation, or as a temperature event interrupt output for microprocessor-based systems. the sensor uses an industry standard 2-wire, i 2 c/smbus serial interface, and allows up to eight devices to be controlled on the bus. typical server or laptop applications total number of sensors is application dependent thermal controller or board management controller or any other i2c/smbus master device mch local temperature sensor event local temperature sensor smbus event smbus features ? temperature sensor ? single supply: 1.7v to 1.9v ? accurate timeout support - meets strict smbus spec of 25ms (min) 35ms (max) ? timeout supported in all modes ? active mode ? shutdown mode ? schmitt trigger and noise filtering on bus inputs ? 2-wire serial interface: 10-400 khz i 2 c? /smbus? ? available package: tdfn-8 temperature sensor features ? temperature converted to digital data ? sampling rate of 100ms (max) ? selectable 0, 1.5c, 3c, 6c hysteresis ? programmable resolution from 0.0625c to 0.5c ? accuracy: ? 0.5c/ 1.0c (typ/max)from +75c to +95c ? 1.0c/2.0c (typ/max) from +40c to +125c ? 2.0c/ 3.0c (typ/max) from -40c to +125c typical applications ? ssd boards ? servers, laptops, ultra-portables, pc boards ? high end audio / video equipment ? portable devices ? hard disk drives and other pc peripherals TS3000GB0A0 data sheet 1.8v local temperature sensor
2 of 25 november 4, 2014 idt block diagram: temperature sensor
3 of 25 november 4, 2014 idt maximum ratings stressing the device above the rating listed in the absolute maxi mum ratings table may cause per manent damage to the device. th ese are stress ratings only and operation of the device at th ese or any other conditions above those indi cated in the operating sections of th is specification is not implied. exposure to absolute maximum rating condi tions for extended periods may affect device reliability. absolute maximum ratings dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the paramete rs in the dc and ac characteristic tables that follow are derived from tests performed under the m easurement conditions summarized in the re levant tables. designers should check that the operating conditions in their ci rcuit match the measurement conditions when relying on the quot ed parameters. dc characteristics operating conditions symbol parameter min. max. units t stg storage temperature -65 150 ? c v io input or output range, sa0 -0.50 10 v input or output range, other pins -0.50 4.3 v v dd supply voltage -0.5 4.3 v symbol parameter min. max. units v dd supply voltage 1.7 1.9 v t a ambient operating temperature -40 +125 ? c
4 of 25 november 4, 2014 idt ac measurement conditions ac measurement i/o waveform input parameters for the TS3000GB0A0 1.t a =25c, f=400 khz 2.verified by design and characterization not necessarily tested on all devices symbol parameter min. max. units c l load capacitance 100 pf input rise and fall times 50 ns input levels 0.2*v dd to 0.8*v dd v input and output timing reference levels 0.3*v dd to 0.7*v dd v symbol parameter 1,2 test condition min. max. units c in input capacitance (sda) 8 pf c in input rise and fall times 6 ns z eil ei (sa0,sa1,sa2) input impedance v in < 0.3* v dd 30 k? z eih ei (sa0,sa1,sa2) input impedance v in > 0.7* v dd 800 k? t sp pulse width ignored (input filter on scl and sda) single glitch, f < 100 khz 100 ns single glitch, f> 100 khz 50
5 of 25 november 4, 2014 idt dc characteristics parameter symbol conditions min. max. units input leakage current i li v in = v ss or v dd 1 ? a output leakage current i lo v out = v ss or v dd , sda in hi-z 1 ? a supply current, temp sensor active i dd v ddspd = 1.8 v, f c = 100 khz (rise/fall time < 30 ns) 500 ? a standby(shutdown) supply current i dd1 v in = v ss or v dd , vdd= 1.9 v 40 ? a input low voltage (scl, sda) v il -0.5 0.3*v dd v input high voltage (scl, sda) v ih 0.7* v dd v dd +1 v sa0 high voltage v hv v hv - v dd > 4.8 v 7 10 v output low voltage v ol i ol = 2.1 ma, 1.7v =< v dd =< 1.9 v 0.4 v i ol = 0.7 ma, v dd = 1.7 - 1.9v 0.2 v input hysteresis v hyst v dd > 2.2v 0.05 * v dd __ v
6 of 25 november 4, 2014 idt ac characteristics 1. for a restart condition, or following a write cycle. 2. guaranteed by design and charact erization, not n ecessarily tested. 3. to avoid spurious start and stop cond itions, a minimum delay is placed between falling edge of scl and the falling or rising edge of sda. 4. the TS3000GB0A0 does not initiate clock stretching which is an optional i 2 c bus feature 5. devices participating in a transfer ca n abort the transfer in prog ress and release the bus when any single clock low interva l exceeds the value of t timeout,min . after the master in a transaction detects this condition, it must generate a stop condition within or after the current data byte in the transfer process. devices that have detected this condition must reset their communication and be able to receive a new start condition no later than t timeout,max . typical device examples include the host controller and embedded controller and most devices that can master the sm bus. some devices do not contain a clock low drive circuit; this simple kind of device typically may re set its communications port after a start or stop condition. a timeout condition can only be ensured if the device that is forcing the timeout holds scl low for t timeout,max or longer. 6. the temperature sensor family of devices ar e not required to support the smbus alert function. parameter 3,6 symbol v dd > 1.7 v units min. max. clock frequency f scl 10 400 khz clock pulse width high time t high 600 ns clock pulse width low time t low 4 1300 ns detect clock low timeout, capabilities register bit 6 =1 t timeout 5 25 35 ms sda rise time t r 2 20 300 ns sda fall time t f 2 20 300 ns data in setup time t su:dat 100 ns data in hold time t hd:di 0n s data out hold time t hd:dat 200 900 ns start condition setup time t su:sta 1 600 ns start condition hold time t hd:sta 600 ns stop condition setup time t su:sto 600 ns time between stop condition and next start condition t buf 1300 ns write time t w 4.5 ms
7 of 25 november 4, 2014 idt temperature-to-digital conversion performance 1v ddspdmin < v ddspd < v ddspdmax . temperature conversion time parameter typ max unit test conditions 1 temperature sensor accuracy 0.5 1.0 c 75c < t a < 95c 1.0 2.0 c 40c < t a < 125c 2.0 3.0 c -40c < t a < 125c resolution adc setting t conv (typ) t conv (max) unit 0.5c 9 bit 100 ms 0.25c 10 bit 100 ms 0.125c (por default) 11 bit 100 ms 0.0625c 12 bit 100 ms
8 of 25 november 4, 2014 idt pin assignment pin description pin functional descriptions serial clock (scl) this input signal is used to strobe all data in and out of the device. in applications where th is signal is used by slave devic es to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor can be connected from serial clock (sc l) to v dd . (refer to the maximum r l value vs. bus capacitance figure on how the value of the pull- up resistor can be calculated). in most applications, though, th is method of synchronization is not employed, and so the pull-up resist or is not necessary, provided that the bus master has a pus h-pull (rather than open drain) output. serial data (sda) this bi-directional signal is us ed to transfer data in or out of the device. it is an open drain output that may be wire-ored w ith other open drain or open collector signals on the bus. a pull up resistor must be c onnected from serial data (sda) to the most positive v dd in the i 2 c chain. (refer to the maximum r l value vs. bus capacitance figure on how the val ue of the pull-up resistor can be calculated). pin # pin name definition 1 sa0 select address 0 2 sa1 select address 1 3 sa2 select address 2 4v ss ground 5sdaserial data in 6 scl serial clock in 7 event temperature event out 8v dd supply voltage sa0 sa1 sa2 vss vdd event scl sda 2 4 1 3 5 7 6 8 sa0 sa1 sa2 vss vdd event scl sda 2 4 1 3 5 7 6 8 sa0 sa1 sa2 vss vdd event scl sda 2 4 1 3 5 7 6 8
9 of 25 november 4, 2014 idt maximum r l value vs. bus capacitance (c bus ) for an i 2 c bus select address (sa0, sa1, sa2) these input signals are used to set the value that is to be look ed for on the three least signific ant bits (b3, b2, b1) of the 7-bit slave address. in the end application, sa0, sa1 and sa2 must be directly (not through a pull-up or pull-down resistor) connected to v dd or v ss to establish the slave address. when these inputs are not connected, an internal pull-down circuitry makes (sa0, sa1, sa2) = (0, 0, 0). event the TS3000GB0A0 event pin is an open drain output t hat requires a pull-up to v dd on the system motherboard or integrated into the master controller. the TS3000GB0A0 event pin has three operating modes, dep ending on configuration settings and any current out-of-limit conditions. these modes are interrupt, comparator, or tcrit only. in interrupt mode the event pin will remain asserted until it is released by writing a '1 ' to the ?clear event? bit in the status register. the value to write is independent of the event polarity bit. in comparator mode the event pin will clear itself when the error condition that caused the pin to be asserted is removed. when the temperature is compared against the tcrit limi t, then this mode is always used. finally, in the tcrit only mode the event pin will only be asserted if the measured temper ature exceeds the tcrit limit. once the pin has been asserted, it will remain asserted until the temperature drops bel ow the tcrit limit minus the tc rit hysteresis. the next figure illustrates the opera- tion of the different modes over time and temperature. systems that use the active high mode for event must be wired point to point between the ts 3000gb0a0 and the sensing controller. wire-or configurations should not be used with active high event since any device pulling the event signal low will mask the other devices on the bus. also note that the normal state of event in active high mode is a 0 which will continually draw power through the pull-up resistor.
10 of 25 november 4, 2014 idt event pin mode functionality
11 of 25 november 4, 2014 idt serial communications the TS3000GB0A0 temperature sensor circuitry continuously monito rs the temperature and updates t he temperature data minimum of eight times per second. temperature data is latched inte rnally by the device and may be read by software from the bus host at any time. internal registers are used to configure both the ts performance and response to over-temperature conditions. the device contai ns programmable high, low, and critical temperature limits. finally, the device event pin can be configured as active high or active low and can be configured to operate as an interrupt or as a comparator output. device diagram smbus/i 2 c communications the data registers in this device are selected by the pointer register. at power-up the pointer register is set to ?00?, the location for the capability register. the pointer register latches the last location it was set to. each data register falls into one of three types of use r accessibility: 1. read only 2. write only 3. write/read same address a write to this device will always include the address byte and t he pointer byte. a write to any register, other than the point er register, requires two data bytes. reading this device can take place either of two ways: if the location latched in the pointer register is correct (most of the time it is expected that the pointer register will poin t to one of the read temperature registers because that will be the data most frequently read), then the read can simply consist of an address byte, followed by retrieving the two data bytes. if the pointer register needs to be set, then an address byte, pointer byte, repeat start, and another address byte will accomp lish a read. the data byte has the most significant bit first. at the end of a read, this device can accept eit her acknowledge (ack) or no a cknowledge (no ack) from the master (no acknowledge is typically used as a signal for the slave that the master has read its last byte). sa0 sa1 sa2 vdd vss event scl sda sa0 sa1 sa2 vdd vss event scl sda TS3000GB0A0
12 of 25 november 4, 2014 idt smbus/i 2 c write to the pointer register smbus/i 2 c write to the pointer register followed by a write data word smbus/i 2 c word read from register with a preset pointer
13 of 25 november 4, 2014 idt smbus/i 2 c write to pointer register followed by a repeat start and an immediate data word read smbus/i 2 c write to the configuration register to enable shutdown ((shdn) <0000 0001 0000 0000>b
14 of 25 november 4, 2014 idt smbus/i 2 c slave sub-address decoding the physical address for ts is different t han that used by current spd devices. the ph ysical address for thermal sensor is ?0 0 1 1 a2 a1 a0 rw? in binary, where a2, a1, a0 are the thr ee slave sub-address pins, and the least signi ficant bit ?rw? is the read/write flag. assuming the slave base address of the spd+ts interface is fixed, for example at 0x30, then the pins set the sub-address bits o f the slave address, allowing the device to be located anywhere within 8 slave address locations, for example from 0x30 to 0x3e. slave address decoding the meaning of the a0/a1/a2 pin states is as follows:; 0= pu ll-down to thermal sensor vss, 1=pull-up to thermal sensor vdd slave address a2 a1 a0 x0 0 0 0 x2 0 0 1 x4 0 1 0 x6 0 1 1 x8 1 0 0 xa 1 0 1 xc 1 1 0 xe 1 1 1
15 of 25 november 4, 2014 idt smbus/i2 ac timing consideration in order for this device to be both smbus and i 2 c compliant, the device complies with a subset of each specification. this requires a few minor considerations to ensure interoperability. the time out requirements of smbus are opti onal for this device. the minimum clock f requency of smbus is a required feature. note that t he minimum data hold time (thd:dat) of 200 ns is smaller than the 300 ns of t he smbus specification. with these minor considerations, this device is capable of co-existing with devices on either an smbus or an i 2 c bus. ts register set definition the register set address are shown in the acknowledge when writing data or defining wr ite protection table. these values are used in the i 2 c operations as the ?reg_ptr? as shown in previous figures.
16 of 25 november 4, 2014 idt temperature register addresses capabilities register the capabilities regist er indicates the supported features of the temperature sensor. capabilities register bits 15 - bit 8 ? rfu; reserved for future use. these bits will alwa ys read '0' and writing to them will have no affect. bit 7- evsd-event with shutdown action. ?0? - (default) the event output freezes in its current state when ent ering shutdown. upon exiting shutdown, the event output remains in the previous state until the next thermal samp le is taken, or possibly sooner if event is programmed for comparator mode. ?1? the event output is deasserted (not driven) when entering shutdown and re mains deasserted upon exit from shutdown until the next thermal sample is taken, or possibly sooner if event is programmed for comparator mode. bit 6 - tmout ? bus timeout period for ther mal sensor access during normal operation. note that the TS3000GB0A0 supports timeout in both active and shutdown mode for temperature sens or and spd (eeprom) portions of the device. ?0? - parameter t timeout is supported within the range of 10 to 60 ms. ?1? - (default) parameter t timeout is supported within the range of 25 to 35 ms (smbus compatible). bit 5 - x ? may be 0 or 1; applications must accept either code. (default =1) bits 4 - 3 ? tres[1:0]; indicates the resolution of the temperatur e monitor as shown in the tres bit decode table. (default =01 ) addr r/w name function default n/a w address pointer address stor age for subsequent operations 00 00 r capabilities indicates the functions and capabilities of the temperature sensor 0077 01 r/w configuration controls the operation of the temperature monitor 0000 02 r/w high limit temperature high limit 0000 03 r/w low limit temperature low limit 0000 04 r/w tcrit limit criti cal temperature 0000 05 r ambient temperature curre nt ambient temperature n/a 06 r manufacturer id pci- sig manufacturer id 00b3 07 r device/revision device id and revision number 2913 08 r/w resolution register allows changing temperature sensor resolution 0010 addr r/w b15/b7 b14/b6 b13/b5 b12/b4 b11/b3 b10/b2 b9/b1 b8/b0 default 00 r rfu rfu rfu rfu rfu rfu rfu rfu 0077 evsd tmout x tres[1:0] range acc event
17 of 25 november 4, 2014 idt tres bit decode note: refer to section resolution register on page 22. bit 2 - range; indicates t he supported temperature range. '0' - the temperature monitor clamps values lower than 0 c. '1' (default) - the temperature moni tor can read temperatures below 0 c and sets the sign bit appropriately. bit 1 - acc; indicates the s upported temperature accuracy. '0' - not used. '1' (default) the temperature monitor has 1 c accuracy over the active range (75c to 95c) and 2c accuracy over the monito ring range (40c to 125c) bit 0 - event ; indicates whether the temperature m onitor supports interrupt capabilities '0'.-the device does not support interrupt capabilities. '1' (default); the device supports interrupt capabilities. configuration register configuration register the configuration register holds the control and status bits of the event pin as well as general hysteresis on all limits. bits 15 - 11 ? rfu; reserved for future use. these bits will al ways read '0' and writing to them will have no affect. for future compatibility, all rfu bits must be programmed as '0'. bits 10 - 9 ? hyst[1:0]; control t he hysteresis that is applied to all limits as shown in the hyst bit decode table that follow s. this hysteresis applies to all limits when the temperature is dropping below the threshold so that once the temperature is above a given thresh old, it must drop below the threshold minus the hysteresis in order to be flagged as an interrupt event. no te that hysteresis is also applied to event pin functionality. when either of the lock bits is se t, these bits cannot be altered. tres[1:0] temperature resolution 10 0 0 0.5c (9-bit) 0 1 0.25c (10-bit) 1 0 0.125c (11-bit) (default) 1 1 0.0625c (12-bit) addr r/w b15/b7 b14/b6 b13/b5 b12/b4 b 11/b3 b10/b2 b9/b1 b8/b0 default 01 r/w rfu rfu rfu rfu rfu hyst[1:0] shdn 0000 tcrit_ lock event_ lock clear event_ sts event_ ctrl tcrit_ only event_ pol event_ mode
18 of 25 november 4, 2014 idt hysteresis t u = value stored in alarm temperature upper boundary trip register t l =value stored in alarm temperature lower boundary trip register hyst= absolute value of selected hysteresis hyst bit decode bit 8 ? shdn-shutdown. the thermal sensi ng device and a/d converters are disabled to save power, no events will be generated. w hen either of the lock bits is set, this bit cannot be set until unlocked. however it can be cleared at any time. when in shutdown mode, the TS3000GB0A0 still responds to commands normally, however bus timeout may or may not be supported in this mode. '0' (default); the temperature monitor is active and converting '1'; the temperature monitor is disabled and will not generate interrupts or update the temperature data. bit 7 ? tcrit_lock; locks the tcrit limit register from being updated. '0' (default; the tcrit limit regi ster can be updated normally. '1'; the tcrit limit register is locked and cannot be updated. once this bit ha s been set, it cannot be cleared until an intern al power on reset. hyst[1:0] hysteresis 10 0 0 disable hysteresis (default) 0 1 1.5c 1 0 3c 1 1 6c
19 of 25 november 4, 2014 idt bit 6 ? event_lock; locks the high and low limit registers from being updated. '0' (default); the high and low lim it registers can be updated normally. '1'; the high and low limit registers are lo cked and cannot be updated. once this bit has been set, it cannot be cleared until an internal power on reset. bit 5 ? clear; clears the event pin when it has been asserted. this bi t is write only and will always read '0'. '0'; does nothing '1'; the event pin is released and will not be asserted until a new in terrupt condition occurs. this bit is ignored if the device is operating in comparator mode. this bit is self clearing. bit 4 ? event_sts; indicates if the event pin is asserted. this bit is read only. ?0' (default); the event pin is not asserted. '1'; the event pin is being asserted by the device. bit 3 ? event_ctrl; masks the event pin from generating an interrupt. if either of the lock bits are set (bit 7 and bit 6), then this bit cannot be altered. '0' (default); the event pin is disabled and will not generate interrupts. '1'; the event pin is enabled. bit 2 ? tcrit_only; controls whether the event pin will be asserted from a high / low out-of-lim it condition. when the event_lock bit is set, this bit cannot be altered. '0' (default); the event pin will be asserted if the measured temperatur e is above the high limit or below the low limit in addition to if the temperature is above the tcrit limit. '1'; the event pin will only be asserted if the measur ed temperature is ab ove the tcrit limit. bit 1 ? event_pol; controls the ?active? state of the event pin. the event pin is driven to this state when it is asserted. '0' (default); the event pin is active low. the ?active? stat e of the pin will be logical '0'. '1'; the event pin is active high. the ?active? stat e of the pin will be logical '1'. bit 0 ? event_mode; controls the behavior of the event pin. the event pin may function in either comparator or interrupt mode. '0'; the event pin will function in comparator mode. '1'; the event pin will function in interrupt mode. temperature register value definitions temperatures in the high limit register, low limit register, tcrit register, and temper ature data register are expressed in two's complement format. bits b12 through b2 for each of these registers are def ined for all device resolutions as defined in the tres field of the capabilities register, hence a 0.25c minimum granularity is supported in all registers. examples of valid settings and interpretation of temperature register bits: temperature register coding examples b15~b0 (binary) value units xxx0 0000 0010 11xx +2.75 c xxx0 0000 0001 00xx +1.00 c xxx0 0000 0000 01xx +0.25 c xxx0 0000 0000 00xx 0 c
20 of 25 november 4, 2014 idt the tres field of the capabiliti es register optionally defines higher resoluti on devices. for compatibility and simplicity, this additional resolution affects only the temperature data register but none of the limi t registers. when higher resolution devices generate status or e vent changes, only bits b12 through b2 are used in the comparis on; however, all 11 bits (tres[1-0] = 10) or all 12 bits (tres[1-0] = 11) are visib le in reads from the temperature data register. when a lower resolution device is indicated in the capabilities register (tres[1-0] = 00), the finest resolution supported is 0 .5c. when this is detected, bit 2 of all limit registers s hould be programmed to 0 to assure correct operation of the temperature comparators. high limit register the temperature limit registers (high, low, and tcrit) define the temperatures to be used by various on-chip comparators to det ermine device temperature status and thermal events. for future com patibility, unused bits ?-? must be programmed as 0. high limit register the high limit register holds the high li mit for the nominal operating window. when the temperature rises above the high limit, or drops below or equal to the high limit, then the event pin is asserted (if enabled). if the event_lock bit is set as shown in the configurat ion register table), then this register becomes read-only. low limit register low limit register the low limit register holds t he lower limit for the nominal operating window. w hen the temperature drops below the low limit o r rises up to meet or exceed the low limit, then the event pin is asserted (if enabled). if the event_lock bit is set as shown in the configuration register, then this register becomes read-only. xxx1 1111 1111 11xx -0.25 c xxx1 1111 1111 00xx -1.00 c xxx1 1111 1101 01xx -2.75 c addr r/w b15/b7 b14/b6 b13/b5 b12/b4 b 11/b3 b10/b2 b9/b1 b8/b0 default 02 r/w ? ? ? sign 128 64 32 16 0000 8 4 2 1 0.5 0.25 ? ? addr r/w b15/b7 b14/b6 b13/b5 b12/b4 b 11/b3 b10/b2 b9/b1 b8/b0 default 03 r/w ? ? ? sign 128 64 32 16 0000 8 4 2 1 0.5 0.25 ? ? temperature register coding examples b15~b0 (binary) value units
21 of 25 november 4, 2014 idt tcrit limit register tcrit limit register the tcrit limit register holds the tcrit limit. if the temperature exceeds the limit, the event pin will be asserted. it will remain asserted until the temperature drops below or equal to the limit minus hysteresis. if the tcrit_lock bit is set as shown in the configuration register table, then this register becomes read-only. temperature data register temperature data register * resolution defined based on value of tres field of the capabilities register. unused/unsupported bits will read as 0. the temperature data register holds the 10- bit + sign data for the internal temperature measurement as well as the status bits indicating which error conditions, if any, are active. the enc oding of bits b 12 through b0 is the same as for the temperature limit registers. bit 15 ? tcrit; when set, the temperature is above the tcrit limi t. this bit will remain set so long as the temperature is abov e tcrit and will automatically clear once the te mperature has dropped below the limit minus the hysteresis. bit 14 ? high; when set, the temperature is above the high limit. this bit will remain set so long as the temperature is above the high limit. once set, it will only be cleared when the te mperature drops below or equal to the high limit minus the hysteresis. bit 13 ? low; when set, the temperature is bel ow the low limit. this bit will remain se t so long as the temperature is below th e low limit minus the hysteresis. once set, it will only be cleared w hen the temperature meets or exceeds the low limit. manufacturer id register manufacturer id register the manufacturer id register holds the pci sig number assigned to the specific manufacturer. device id/revision register device id/revision register the upper byte of the device id / revision register stores a unique number indicating the TS3000GB0A0 from other devices. the lower byte holds the revision value. addr r/w b15/b7 b14/b6 b13/b5 b12/b4 b 11/b3 b10/b2 b9/b1 b8/b0 default 04 r/w ? ? ? sign 128 64 32 16 0000 8 4 2 1 0.5 0.25 ? ? addr r/w b15/b7 b14/b6 b13/b5 b12/b4 b 11/b3 b10/b2 b9/b1 b8/b0 default 05 r tcrit high low sign 128 64 32 16 n/a (0000) 8 4 2 1 0.5 0.25* 0.125* 0.0625* addr r/w b15/b7 b14/b6 b13/b5 b12/b4 b 11/b3 b10/b2 b9/b1 b8/b0 default 06 r/w 00000 0 00 00b3 10110 0 11 addr r/w b15/b7 b14/b6 b13/b5 b12/b4 b 11/b3 b10/b2 b9/b1 b8/b0 default 07 r/w 00101 0 01 2913 00010 0 10
22 of 25 november 4, 2014 idt resolution register this register allows the user to change the resolution of the temperature sensor. the por defaul t resolution is 0.125c. the re solution imple- mented via this register is also re flected in the capability register. resolution register legend: resolution bits 4-3 tres[4:3] 00 = lsb = 0.5c (register value = 0007) 01 = lsb = 0.25c (register value = 000f) 10 = lsb = 0.125c (register value = 0017) 11 = lsb = 0.0625c (register value = 001f) conversion times for each resolution are less than 100ms (worst case). addr r/w b15/b7 b14/b6 b13/b5 b12/b4 b11/b3 b10/b2 b9/b1 b8/b0 default value 08hr/w000000000010 0 0 0 tres[1] tres[0] 0 0 0
23 of 25 november 4, 2014 idt
24 of 25 november 4, 2014 idt
25 of 25 november 4, 2014 idt ? corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: email: memorymodule-help@idt.com phone: 408-284-8208 ordering information example: TS3000GB0A0 ncg8 xxxxx x x rev. voltage shipping 8 tape and reel x device type 3000g temperature sensor x temp b temperature accuracy grade carrier ts range 0 a0 xxx package ncg green tdfn (2.0 x 3.0mm body, 0.75mm thick) (1.7v to 1.9v )

▲Up To Search▲

Price & Availability of TS3000GB0A0

	To Download TS3000GB0A0 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .